The present invention relates to a semiconductor memory having a memory cell array needing an operation called refresh, and particularly relates to an improvement in a refresh control circuit.
It is generally known that refresh is essential to dynamic random access memories (DRAMs) having memory cells formed by respective capacitors. A typical DRAM refresh control circuit employs RAS (row address strobe) and CAS (column address strobe) signals. More specifically, there are some refresh methods including a RAS-only refresh and a CBR (CAS-before-RAS) refresh.
Self-refresh is suitable for power-down modes such as a DRAM battery back-up mode. In the DRAM, an internal timer automatically generates refresh request signal pulses at periodic intervals and an internal counter automatically generates refresh addresses. CBR self-refresh is the current standard specification, wherein in a CBR refresh, a self-refresh mode is made to begin by maintaining both RAS and CAS signals at their activation level (LOW level) for 100 microseconds or more.
A conventional semiconductor memory is configured to perform a refresh operation on the basis of RAS and CAS signals received from a logic circuit for controlling access of the semiconductor memory. This accordingly requires the logic circuit to perform sophisticated control operations such as controlling timing of generating a leading edge of a first pulse to be applied as a CAS signal, a leading edge of a second pulse to be applied as a RAS signal, and a trailing edge of the second pulse.